1. Field of the Invention
The present invention concerns an integrated circuit (“IC”) device having network paths, wherein some of the network paths have associated non-compute (“N/C”) indications produced by a timing analysis run. More specifically, it concerns selecting, before a subsequent timing run, those N/C-indicated network paths in which circuitry is changed.
2. Description of Background
A timing analysis run for an IC chip design commonly designates many nets in the design as N/C's. Some N/C's are expected, while some are problems. Those that are problems must be fixed. Many of them, however, are OK. It may happen that they are OK for a variety of reasons. Sometimes the logic designer intentionally left an input tied off or an output disconnected, for example. In a large IC chip design, there may be many thousands of these N/C indications for a timing run. Sometimes there may be tens of thousands, or even hundreds of thousands of N/C's. Thus, in order to confirm whether all necessary paths were timed in the run, it is conventional to manually examine long lists of N/C's generated by the timing run and to manually separate N/C's that do exist for valid and understood reasons from ones that do not. This is, of course, problematic, because this manual process is both resource intensive and subject to error.